A. V. Garashchenko, L. G. Gagarina Research and Development of the Algorithm for generating a Test Sequence for Evaluating the Power Consumption of an RTL-Model of Processor
A. V. Garashchenko, L. G. Gagarina Research and Development of the Algorithm for generating a Test Sequence for Evaluating the Power Consumption of an RTL-Model of Processor

One of the most important trends in the development of modern microelectronics, due to a decrease in the technological process of semiconductor production and an increase in the degree of integration of microcircuits, is an increase in the performance of computer systems by increasing heterogeneity, but the energy consumption in different operating modes is a limiting factor. The article discusses the task of forming a test sequence that provides maximum switching activity for all processor units. This task belongs to the class of those problems whose complexity grows exponentially with an increasing number of input data (the number of instructions in the ISA and the dependencies between them). However, its solution can be reduced to solving the discrete optimization problem. A mathematical model is proposed for maximizing the objective function of switching activity using a genetic algorithm, for the parallel launch of which a modified architecture of the island model based on a cellular automaton is considered. The implementation of crossbreeding, mutation, and migration operators is theoretically justified. Using the algorithm, a test sequence for the developed VLIW DSP processor with RISC architecture is formed.


verification, processors, power consumption, genetic algorithm, cellular automata, parallel algorithms.

DOI 10.14357/20718632200309

PP. 94-100.

1. Ajay M. Joshi, Lieven Eeckhout, Lizy K. John, Ciji IsenCiji Isen, Automated Microprocessor Stressmark Generation, Conference: High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium.
2. Formal Verification of Floating-Point RTL at AMD Using the ACL2 Theorem Prover David M. Russinoff.
3. Y. Kim and L. K. John, Automated di/dt stressmark generation for microprocessor power delivery networks, IEEE/ACM International Symposium on Low Power Electronics and Design, Fukuoka, 2011, pp. 253-258, doi: 10.1109/ISLPED.2011.5993645.
4. Alexandre Otto Strube, Dolores Rexachs, Emilio Luque, Software Probes: A Method for Quickly Characterizing Applications Performance on Heterogeneous Environments, Parallel Processing Workshops 2009. ICPPW '09. International Conference on, pp. 262-269, 2009.
5. Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog Hardcover, Springer – May 31, 2001.
6. Kamkin A., Kotsynyak A., Smolov S., Tatarnikov A., Chupilko M., Sortov A., Means of functional verification of microprocessors // Proceedings of the Institute for System Programming of the Russian Academy of Sciences, 2014, Vol. 26, No. 1, pp. 149–206.
7. Garashchenko A., Nikolaev A., Putrya F., Sardaryan S., System of combined specialized test generators for a new generation of VLIW DSP processors with Elcore50 architecture // Problems of developing promising micro- and nanoelectronic systems. 2018. №2. C. 9–15.
8. Putrya F., The use of random program generators and random background effects in the functional verification of multicore systems on a chip // Computer-aided design of discrete systems. 2010, C. 234 –241.
9. Gagarina L., Garashchenko A., Shiryaev A., Fedorov A. Dorogova E., An approach to automatic test generation for verification of microprocessor cores // Young Researchers in Electrical and Electronic Engineering (EIConRus), 2018, C. 1490–1491.
10. Shamsul Alam S., Performance Analysis of LT Codec Architecture Using Different Processor Templates // International Journal of Information Technology and Computer Science(IJITCS), 2019, №.8, С.41–48.
11. Kamath A., Automatic Verification of Microprocessor designs using Random Simulation // Computer Science, 2012, C 1–5.
12. Lagoon V, Constraint-Based Test Generation // Cadence, 2012, C. 1.
13. Litterick M., Harnisch M., Advanced UVM Register Modeling // Cadence, 2012, C. 1.
14. Ershov N.M., N.N. Popova, Natural models of parallel computing // Computer Research and Modeling. 2015, Vol. 7, No. 3, pp. 781–785.
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