
V. S. Potapov, S. M. Gushansky Development of a Method for Constructing a Quantum System Using Optimization Hardware 

Abstract.
The paper developed and simulated a hardware computing core, which is the main part of the accelerator based on fieldprogrammable logic integrated circuits with the Altera Quartus computeraided design system. Taking into account the obtained time dependence of the number of cycles required for the impact of a singlequbit quantum gate on a quantum register on the number of qubits and parallel arithmetic logic units in the hardware computing core, when simulating quantum computing, a method was developed to determine the estimate of the increase in hardware performance and ways to increase the performance of the accelerator based on hardware computing core based on programmable logic integrated circuits. A comparative analysis of the methodology for optimizing the simulation of quantum computing and mathematical modeling was also carried out.
Keywords:
quantum algorithm, quantum bit, quantum circuit, entanglement, register, gate, parallelism, quantum computer.
PP. 2632.
DOI 10.14357/20718632220103 References
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